The present invention is directed to integrated circuits and their processing for the manufacture of semiconductor devices. More particularly, the invention provides a method for improving the adhesion strength of low dielectric strength dielectric layers used in the fabrication of semiconductor devices. But it would be recognized that the invention has a much broader range of applicability. Certain embodiments of the invention can be applied to microprocessor devices, memory devices, application specific integrated circuit devices, as well as various other interconnect structures.
Integrated circuits or “ICs” have evolved from a handful of interconnected devices fabricated on a single chip of silicon to millions of devices. Current ICs provide performance and complexity far beyond what was originally imagined. In order to achieve improvements in complexity and circuit density (i.e., the number of devices capable of being packed onto a given chip area), the size of the smallest device feature, also known as the device “geometry”, has become smaller with each generation of ICs. Semiconductor devices are now being fabricated with features less than a quarter of a micron across.
Increasing circuit density has not only improved the complexity and performance of ICs but has also provided lower cost parts to the consumer. An IC fabrication facility can cost hundreds of millions, or even billions, of dollars. Each fabrication facility will have a certain throughput of wafers, and each wafer will have a certain number of ICs on it. Therefore, by making the individual devices of an IC smaller, more devices may be fabricated on each wafer, thus increasing the output of the fabrication facility. However, one significant problem that occurs with shrinking figure sizes on an IC is that the conducting portions of an IC such as wire interconnects and transistors often need to be placed closer and closer together, and the insulating dielectrics used to separate the conducting portions also become thinner to accommodate for the reduced size between conducting portions. However, as the transistors are placed in greater proximity to each other, problems in cross-talk noise, power dissipation, RC delay and others can occur.
One design implementation choice that can help alleviate the problems described above as a result of more tightly packed IC layouts is the use of low-k dielectrics between the conducting portions of the IC. For example, low-k dielectrics have a k-value or dielectric constant of below 3.0. Their use can result in lower parasitic capacitance and enable faster switching speeds and lower heat dissipation within the IC. However, the incorporation of low-k dielectric materials into IC chips can result in integration difficulties not previously foreseen.
From the above, it can be seen that an improved technique for processing semiconductor devices is desired.